1. Field of the Invention
The present invention relates to a thin film transistor (hereinafter referred to as a TFT) substrate including a substrate and a large number of TFTs formed thereon used for, for example, an active matrix liquid crystal display device and to a method of manufacturing the same. More particularly, the present invention relates to a structure of the TFT substrate having a gate terminal for supplying a scanning signal from a scanning circuit to a gate electrode of the TFT of a inverted stagger structure, and to a method of manufacturing the same.
2. Description of the Related Arts
FIG. 8 shows an example of the TFT substrate used for an active matrix liquid crystal display device. A large number of TFTs 1 of inverted stagger structure are formed longitudinally and latitudinally on a TFT substrate 2 as shown in the figure. A plurality of gate terminals 18 for supplying scanning signals from a scanning circuit to gate electrodes 12 of the TFTs 1 through a gate wiring, and a plurality of source terminals 19 for supplying data signals from a data circuit to source electrodes of the TFTs 1 through a source wiring are formed on the TFT 2. The gate electrodes 12 of each of the TFTs 1 are electrically connected to the gate terminals 18 through the gate wiring 21, and the each of the source electrodes are electrically connected to the source terminals 19 through the gate wiring 22.
The TFT 1, the gate wiring 21, the source wiring 22, the gate terminal 18 and the source terminal 19 of the conventional TFT substrate 2 are arranged in such a manner as shown in FIG. 9(A). The cross sections of the TFT 1, the gate terminal 18 and the source terminal 19 are formed in such manners as shown in the cross sectional views of the FIGS. 9(B) to 9(D), respectively. FIGS. 9(B) to 9(D) are cross sectional views of FIG. 9(A) taken on lines A--A, B--B and C--C, respectively. A conductive material constituting the gate terminal 18 is formed into a film together with the conductive material constituting the gate electrode 12 and the gate wiring 21.
As shown in FIG. 9(D), the source terminal 19 is formed on a gate insulator 13 which is formed on a substrate 11. Only a passivation film 27 is formed on the conductive material constituting the source terminal 19, and the passivation film 27 formed on the conductive material are processed and removed so that the source terminals 19 can be electrically connected to the terminals of a data circuit.
In contrast to this, since the conductive material constituting the gate terminal 18 is formed into a film together with the gate electrode 12, as shown in FIG. 9(C), it is formed directly on the substrate 11. The gate insulator 13 is formed on the conductive material constituting the gate terminal 18, and the passivation film 27 is formed thereon. Two kinds of these insulating films formed on the gate terminal 18 are processed and removed by a separate process, respectively so as to be electrically connected to the terminals from the scanning circuit. An effective contact width (S0) of the source terminal 19 and an effective contact width (G0) of the gate terminal 18 should be securely connected to the terminals from a driving circuit. Usually, these effective contact widths S0 and G0 are equal (G0=S0).
A width (S1) of the conductive material constituting the source terminal 19 should be longer than the effective contact width (S0) of the source terminal 19, and the difference (S1-S0) between these two widths should be at least two times a sum of process accuracy and a mask alignment accuracy (hereinafter referred to as process accuracy) (C1) (that is to say, S1=S0+C1+C1).
In a similar manner as that described above, a width (G11) of the conductive material constituting the gate terminal 18 should be longer than the effective contact width (G0) of the gate terminal 18, and the difference (G11-G0) between these two widths should be at least two times the process accuracies (C3 and C2) of each of the films (the gate insulator 13 and the passivation film 27 (that is to say, G11=G0+C3+C2+C2+C3). Since each of process accuracies are equal to each other (C1=C2=C3), the width of the conductive material constituting the source terminal 19 {S1=S0+(2.times.C1)} will be different from that of the conductive material constituting the gate terminal 18 {G11=G0+(4.times.C1)}. Thus, when G0 and S0 are equal to each other, the width of the conductive material constituting the gate terminal 18 should be elongated by about two times the process accuracy (2.times.C1).
This difference (2.times.C1) does not affect on the TFT substrate in the case where a large number of the gate terminals 18 can be arranged with wide spaces therebetween. However, in case of the TFT substrate used for the active matrix liquid crystal display device for which densification of display is required, it becomes necessary to narrow the spaces between a large number of the gate terminals 18 arranged on the substrate, and the difference (2.times.C1) becomes a large problem. That is to say, there is a serious problem that the necessary gate terminals 18 cannot be arranged in the limited area and that densification of display is inhibited.